TIE=TIE_0, TPWC=TPWC_0, TF=TF_0, TDRE=TDRE_0, TMODE=TMODE_0
Timer Control Status Register
| TDRE | Timer DMA Request Enable 0 (TDRE_0): DMA request is disabled 1 (TDRE_1): DMA request is enabled |
| TMODE | Timer Mode 0 (TMODE_0): Timer Channel is disabled. 1 (TMODE_1): Timer Channel is configured for Input Capture on rising edge. 2 (TMODE_2): Timer Channel is configured for Input Capture on falling edge. 3 (TMODE_3): Timer Channel is configured for Input Capture on both edges. 4 (TMODE_4): Timer Channel is configured for Output Compare - software only. 5 (TMODE_5): Timer Channel is configured for Output Compare - toggle output on compare. 6 (TMODE_6): Timer Channel is configured for Output Compare - clear output on compare. 7 (TMODE_7): Timer Channel is configured for Output Compare - set output on compare. 9 (TMODE_9): Timer Channel is configured for Output Compare - set output on compare, clear output on overflow. 10 (TMODE_10): Timer Channel is configured for Output Compare - clear output on compare, set output on overflow. 14 (TMODE_14): Timer Channel is configured for Output Compare - pulse output low on compare for 1 to 32 1588-clock cycles as specified by TPWC. 15 (TMODE_15): Timer Channel is configured for Output Compare - pulse output high on compare for 1 to 32 1588-clock cycles as specified by TPWC. |
| TIE | Timer Interrupt Enable 0 (TIE_0): Interrupt is disabled 1 (TIE_1): Interrupt is enabled |
| TF | Timer Flag 0 (TF_0): Input Capture or Output Compare has not occurred. 1 (TF_1): Input Capture or Output Compare has occurred. |
| TPWC | Timer PulseWidth Control 0 (TPWC_0): Pulse width is one 1588-clock cycle. 1 (TPWC_1): Pulse width is two 1588-clock cycles. 2 (TPWC_2): Pulse width is three 1588-clock cycles. 3 (TPWC_3): Pulse width is four 1588-clock cycles. 31 (TPWC_31): Pulse width is 32 1588-clock cycles. |